The present disclosure relates to a semiconductor device and, more particularly, to an address synchronous circuit.
A semiconductor memory device, including a DRAM, has a memory cell array with a plurality of memory cells for storing data and a peripheral circuit for controlling data input/output operations.
The memory cell array forms a matrix which has a plurality of rows and columns, namely, word lines and bit lines. A predetermined address is assigned to each row and column. A row address is used to designate a specific row, and a column address is used to designate a specific column.
Meanwhile, a clock is used as a reference for adjusting operation timing in a system or a circuit. The clock is also used for guaranteeing a faster operation without an error. Examples of such a clock synchronous semiconductor memory device are a SDRAM (Synchronous DRAM) or a DDR SDRAM (Double Data Rate Synchronous DRAM).
FIG. 1 is a block diagram of a conventional address synchronous circuit, and FIG. 2 is a detailed circuit diagram of the address synchronous circuit of FIG. 1.
As shown in FIG. 1, the conventional address synchronous circuit includes an address input buffer unit 100, a setup hold delay unit 200 and an address synchronous unit 300.
As shown in FIG. 2, the address synchronous unit 300 includes a cross-coupled latch unit 301 for synchronizing an address ADD_OUT which is output from the setup hold delay unit 200 with an internal clock signal CLKP4 and a driving unit 302 for pull-up or pull-down driving in response to an output signal of the cross-coupled latch unit 301.
According to the conventional address synchronous circuit, an address ADD is input to the address input buffer unit 100 and then is input to the address synchronous unit 300 via the setup hold delay unit 200. The inputted address is synchronized with the internal clock signal CLKP4 through the cross-coupled latch unit 301.
However, the conventional address synchronous circuit continuously consumes a current because it outputs the address in synchronization with the internal clock signal CLKP4 whenever the address changes. Such an unnecessary current consumption causes an increase in the current consumption in the memory, especially in the DRAM.